Power Optimization Issues in Dual Voltage Design

In this paper, we look at power optimization issues under dual supply voltage environment, with the goal of optimizing power consumption due to interconnection and gate capaci-tances. Logic level synthesis is used as a good starting point for power reduction, while subsequent placement stage mod-iies or veriies logic level design by providing more accurate estimate of power dissipation. We try to reduce power dissipation due to gate capacitance at logic level using two supply voltages. This however imposes a constraint on the placement stage as the nal placement has to conform to the speciic layout structure. We discuss how both levels interact with one another, and propose an eeective algorithm to nd the tradeoo between power reduction and placement legality. Experimental results show that, on an average, a nal power reduction of nearly 16% is obtained by our approach.